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16-bit, 100 ksps, single-ended pulsar adc in msop/qfn data sheet ad7683 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2004C2016 analog devices, inc. all rights reserved. technical support www.analog.com features 16-bit resolution with no missing codes throughput: 100 ksps inl: 1 lsb typical, 3 lsb maximum pseudo differential analog input range 0 v to v ref with v ref up to vdd single-supply operation: 2.7 v to 5.5 v serial interface spi/qspi/microwire/dsp compatible power dissipation: 4 mw @ 5 v, 1.5 mw @ 2.7 v, 150 w @ 2.7 v/10 ksps standby current: 1 na 8-lead packages: msop 3 mm 3 mm qfn (lfcsp) (sot-23 size) improved second source to ads8320 and ads8325 applications battery-powered equipment data acquisition instrumentation medical instruments process control application diagram ad7683 ref gnd vdd +in ?in dclock d out cs 3-wire spi interface 0.5v to vdd 2.7v to 5.5 v 0v to v ref 04301-001 figure 1. table 1. msop, qfn (lfcsp)/sot-23, 14-/16-/18-bit pulsar adc type 100 ksps 250 ksps 400 ksps to 500 ksps 1000 ksps adc driver 18-bit true differential ad7691 ad7690 ad7982 ad7984 ada4941-1 ada4841-1 16-bit true differential ad7684 ad7687 ad7688 ad7693 ada4941-1 ada4841-1 16-bit pseudo differential ad7680 ad7683 ad7685 ad7694 ad7686 ad7980 ada4841-1 14-bit pseudo differential ad7940 ad7942 ad7946 ada4841-1 general description the ad7683 is a 16-bit, charge redistribution, successive approximation, pulsar? analog-to-digital converter (adc) that operates from a single power supply, vdd, between 2.7 v and 5.5 v. it contains a low power, high speed, 16-bit sampling adc with no missing codes (b grade), an internal conversion clock, and a serial, spi-compatible interface port. the part also contains a low noise, wide bandwidth, short aperture delay, track-and-hold circuit. on the cs falling edge, it samples an analog input, +in, between 0 v to ref with respect to a ground sense, Cin. the reference voltage, ref, is applied externally and can be set up to the supply voltage. its power scales linearly with throughput. the ad7683 is housed in an 8-lead msop or an 8-lead qfn (lfcsp) package, with an operating temperature specified from ?40c to +85c.
ad7683* product page quick links last content update: 02/23/2017 comparable parts view a parametric search of comparable parts. evaluation kits ? ad7683 evaluation kit documentation application notes ? an-931: understanding pulsar adc support circuitry ? an-932: power supply sequencing data sheet ? ad7683: 16-bit, 100 ksps, single-ended pulsar adc in msop/qfn data sheet product highlight ? [no title found] product highlight ? 8- to 18-bit sar adcs ... from the leader in high performance analog ? lowest-power 16-bit adc optimizes portable designs (eeproductcenter, 10/4/2006) user guides ? ug-340: evaluation board for the 10-lead family 14-/16-/ 18-bit pulsar adcs ? ug-682: 6-lead sot-23 adc driver for the 8-/10-lead family of 14-/16-/18-bit pulsar adc evaluation boards software and systems requirements ? bemicro fpga project for ad7683 with nios driver ? ad7683 fmc-sdp interposer & evaluation board / xilinx kc705 reference design tools and simulations ? ad7683 ibis models reference materials technical articles ? ms-2210: designing power supplies for high speed adc design resources ? ad7683 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ad7683 engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified.
ad7683 data sheet rev. b | page 2 of 16 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? application diagram ........................................................................ 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? timing specifications .................................................................. 5 ? absolute maximum ratings ............................................................ 6 ? thermal resistance ...................................................................... 6 ? esd caution .................................................................................. 6 ? pin configurations and function descriptions ........................... 7 ? terminology ...................................................................................... 8 ? typical performance characteristics ............................................. 9 ? applications information .............................................................. 12 ? circuit information .................................................................... 12 ? converter operation .................................................................. 12 ? transfer functions ..................................................................... 12 ? typical connection diagram ................................................... 13 ? analog input ............................................................................... 13 ? driver amplifier choice ........................................................... 13 ? voltage reference input ............................................................ 14 ? power supply ............................................................................... 14 ? digital interface .......................................................................... 14 ? layout .......................................................................................... 14 ? evaluating the ad7683 performance ...................................... 14 ? outline dimensions ....................................................................... 15 ? ordering guide .......................................................................... 16 ? revision history 2/16rev. a to rev. b changes to table 1 ............................................................................ 1 added figure 7 and table 9; renumbered sequentially ............. 7 changes to table 10 ........................................................................ 13 changes to digital interface section ............................................ 14 updated outline dimensions ....................................................... 16 changes to ordering guide .......................................................... 16 2/08rev. 0 to rev. a change to title .................................................................................. 1 moved figure 3, figure 4, and figure 5 ......................................... 5 changes to figure 4 .......................................................................... 5 moved figure 17 and figure 18 .................................................... 11 changes to figure 22 ...................................................................... 13 updated outline dimensions ....................................................... 15 changes to ordering guide .......................................................... 16 9/04initial version: revision 0
data sheet ad7683 rev. b | page 3 of 16 specifications vdd = 2.7 v to 5.5 v; v ref = vdd; t a = C 40c to +85c, unless otherwise noted. table 2. parameter conditions ad7683 all grades unit min typ max resolution 16 bits analog input voltage range +in ? ( C in) 0 v ref v absolute input voltage +in ?0.1 vdd + 0.1 v ?in ?0.1 0.1 v analog input cmrr f in = 100 khz 65 db leakage current at 25 c acquisition phase 1 na input impedance see the analog input section throughput speed complete cycle 10 s throughput rate 0 100 ksps dclock frequency 0 2.9 mhz reference voltage range 0.5 vdd + 0.3 v load current 100 ksps, v +in ? v ?in = v ref /2 = 2.5 v 50 a digital inputs logic levels v il ?0.3 0.3 vdd v v ih 0.7 vdd vdd + 0.3 v i il ?1 +1 a i ih ?1 +1 a input capacitance 5 pf digital outputs data format serial, 16 bits straight binary v oh i source = ?500 a vdd ? 0.3 v v ol i sink = +500 a 0.4 v power supplies vdd specified performance 2.7 5.5 v vdd range 1 2.0 5.5 v operating current 100 ksps throughput vdd vdd = 5 v 800 a vdd = 2.7 v 560 a standby current 2 , 3 vdd = 5 v, 25 c 1 50 na power dissipation vdd = 5 v 4 6 mw vdd = 2.7 v 1.5 mw vdd = 2.7 v, 10 ksps throughput 2 150 w temperature range specified performance t min to t max ?40 +85 c 1 see the typical performance characteristics section for more information . 2 wit h all digital inputs forced to vdd or gnd , as required. 3 during acquisition phase.
ad7683 data sheet rev. b | page 4 of 16 vdd = 5 v; v ref = vdd; t a = C 40c to +85c, unless otherwise noted. table 3. parameter conditions a grade b grade unit min typ max min typ max accuracy no missing codes 15 16 bits integral linearity error ?6 3 +6 ?3 1 +3 lsb transition noise 0.5 0.5 lsb gain error 1 , t min to t max 2 24 2 15 lsb gain error temperature drift 0.3 0.3 ppm/c offset error 1 , t min to t max 0.7 1.6 0.4 1.6 mv offset temperature drift 0.3 0.3 ppm/c power supply sensitivity vdd = 5 v 5% 0.05 0.05 lsb ac accuracy signal -to - noise f in = 1 khz 90 88 91 db 2 spurious - free dynamic range f in = 1 khz ?100 ?108 db total harmonic distortion f in = 1 khz ?100 ?106 db signal -to - (noise + distortion) f in = 1 khz 90 88 91 db effective number of bits f in = 1 khz 14.7 14.8 bits 1 see the terminology section. these specifications include full temperature range variation but do not include the error contribution from the external reference. 2 all specifications in db are refer red to a full - scale input , fs. tested with an in put signal at 0.5 db below full scale, unless otherwise specified. vdd = 2.7 v; v ref = 2.5v; t a = C 40c to +85c, unless otherwise noted. table 4. a grade b grade parameter conditions min typ max min typ max unit accuracy no missing codes 15 16 bits integral linearity error ?6 3 +6 ?3 1 +3 lsb transition noise 0.85 0.85 lsb gain error 1 , t min to t max 2 30 2 15 lsb gain error temperature drift 0.3 0.3 ppm/c offset error 1 , t min to t max 0.7 3.5 0.7 3.5 mv offset temperature drift 0.3 0.3 ppm/c power supply sensitivity vdd = 2.7 v
data sheet ad7683 rev. b | page 5 of 16 timing specifications vdd = 2.7 v to 5.5 v; t a = ?40c to +85c, unless otherwise noted. table 5. parameter symbol min typ max unit throughput rate t cyc 100 khz cs falling to dclock low t csd 0 s cs falling to dclock rising t sucs 20 ns dclock falling to data remains valid t hdo 5 16 ns cs rising edge to d out high impedance t dis 14 100 ns dclock falling to data valid t en 16 50 ns acquisition time t acq 400 ns d out fall time t f 11 25 ns d out rise time t r 11 25 ns timing and circuit diagrams 04301-002 d out dclock complete cycle power down cs d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 (msb) (lsb) high-z 0 high-z t acq t dis 0 145 t hdo t en t csd t sucs t cyc notes 1. a minimum of 22 clock cycles are required for 16-bit conversion. shown are 24 clock cycles. d out goes low on the dclock falling edge following the lsb reading. figure 2. serial interface timing 04301-003 500a i ol 500a i oh 1.4v t o d out c l 100pf figure 3. load circuit fo r digital interface timing 0.8v 2v 2v 0.8v 0.8v 2v t en t en 04301-004 figure 4. voltage reference levels for timing 04301-006 d out 90% 10% t r t f figure 5. d out rise and fall timing
ad7683 data sheet rev. b | page 6 of 16 absolute maximum rat ings table 6. parameter rating analog inputs +in 1 , C in 1 gnd ? 0.3 v to vdd + 0.3 v or 130 ma ref gnd ? 0.3 v to vdd + 0.3 v supply voltages vdd to gnd ?0.3 v to +6 v digital inputs to gnd ?0.3 v to vdd + 0.3 v digital outputs to gnd ?0.3 v to vdd + 0.3 v storage temperature range ?65c to +150c junction temperature 150c lead temperature range jedec j - std -20 vapor phase (60 sec) 215c infrared (15 sec) 220c 1 see the analog input section. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at the se or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance table 7 . thermal resistance package type ja jc unit 8- lead msop 200 44 c/w esd caution
data sheet ad7683 rev. b | page 7 of 16 pin configurations and function descriptions 04301-005 ref 1 +in 2 ?in 3 gnd 4 vdd 8 dclock 7 d out 6 cs 5 ad7683 top view (not to scale) figure 6. 8-lead msop pin configuration table 8. 8-lead msop pin function descriptions pin no. mnemonic type 1 function 1 ref ai reference input voltage. the ref range is from 0.5 v to vdd. it is referred to the gnd pin. decouple the ref pin closely to the gnd pin with a ceramic capacitor of a few f. 2 +in ai analog input. it is referred to pin Cin. the voltage ra nge, that is, the difference between +in and Cin, is 0 v to v ref . 3 Cin ai analog input ground sense. co nnect this pin to ei ther the analog ground plane or a remote sense ground. 4 gnd p power supply ground. 5 cs di chip select input. on its falling edge, it initiates th e conversions. the part returns to shutdown mode as soon as the conversion is completed. it also enables d out . when high, d out is high impedance. 6 d out do serial data output. the conver sion result is output on this pin. it is synchronized to dclock. 7 dclock di serial data clock input. 8 vdd p power supply. 1 ai = analog input; di = digital input; do = digital output; and p = power. 04301-107 3 ?in 4 gnd 1 ref 2 +in 6d out 5cs notes 1. exposed pad. connect the exposed pad to gnd. this connection is not required to meet specified electrical performance. 8vdd 7 dclock ad7683 top view (not to scale) figure 7. 8-lead qfn (l fcsp) pin configuration table 9. 8-lead qfn (lfcsp) pin function descriptions pin no. mnemonic type 1 function 1 ref ai reference input voltage. the ref range is from 0.5 v to vdd. it is referred to the gnd pin. decouple the ref pin closely to the gnd pin with a ceramic capacitor of a few f. 2 +in ai analog input. it is referred to pin Cin. the voltage ra nge, that is, the difference between +in and Cin, is 0 v to v ref . 3 Cin ai analog input ground sense. co nnect this pin to ei ther the analog ground plane or a remote sense ground. 4 gnd p power supply ground. 5 cs di chip select input. on its falling edge, it initiates th e conversions. the part returns to shutdown mode as soon as the conversion is completed. it also enables d out . when high, d out is high impedance. 6 d out do serial data output. the conver sion result is output on this pin. it is synchronized to dclock. 7 dclock di serial data clock input. 8 vdd p power supply. epad exposed pad. connect the exposed pad to gnd. this connection is not required to meet specified electrical performance. 1 ai = analog input; di = digital input; do = digital output; and p = power.
ad7683 data sheet rev. b | page 8 of 16 terminology integral nonlinearity error (inl) linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line (see figure 22). differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb ap art. dnl is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. offset error the first transition should occur at a level ? lsb above analog ground (38.1 v for the 0 v to 5 v range). the offset error is the deviation of the actual transition from that point. gain error the last transition (from 111...10 to 111...11) should occur for an analog voltage 1? lsb below the nominal full scale (4.999886 v for the 0 v to 5 v range). the gain error is the deviation of the actual level of the last transition from the ideal level after the offset has been adjusted out. spurious - free dynamic range (sfdr) the difference, in decibels (db), between the rms amplitude of the input signal and t he peak spurious signal. signal - to - (noise + distortion) ratio (sinad) sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the val ue for sinad is expressed in db. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to sinad (as represented by s/(n+d) ) by the following formula and is expressed in bits : [ ] ( ) 02 . 6 / 76 . 1 / ? + = db d n s enob d d d d d db s n sn sn n d d d sn d db d d d d s d d d d d
data sheet ad7683 rev. b | page 9 of 16 typical performance characteristics 3 2 1 0 ?1 ?2 ?3 0 16384 32768 49152 65536 04301-012 code inl (lsb) positive inl = +0.43lsb negative inl = ?0.97lsb figure 8. integral nonlinearity vs. code 7000 6000 5000 4000 3000 2000 1000 0 79fd79fe79ff7a007a017a027a037a047a057a067a077a08 04301-009 code in hex counts vdd = ref = 2.5v 001 4604 130 00 2755 25440 50 62564 35528 figure 9. histogram of a dc input at the code center 0 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 1020304050 04301-008 frequency (khz) amplitude (db of full scale) 16384 point fft vdd = ref = 5v f s = 100ksps f in = 20.43khz snr = 92.7db thd = ?105.7db sfdr = ?106.4db figure 10. fft plot 3 2 1 0 ?1 ?2 ?3 0 16384 32768 49152 65536 04301-011 code dnl (lsb) positive dnl = +0.43lsb negative dnl = ?0.41lsb figure 11. differential nonlinearity vs. code 120000 100000 80000 60000 40000 20000 0 7a0e 7a0f 7a10 7a11 7a 12 7a13 7a14 7a15 7a16 04301-010 code in hex counts 006 00 102287 13619 15152 8 vdd = ref = 5v figure 12. histogram of a dc input at the code center 0 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 1020304050 04301-007 frequency (khz) amplitude (db of full scale) 16384 point fft vdd = ref = 2.5v f s = 100ksps f in = 20.43khz snr = 88.7db thd = ?102.6db sfdr = ?104.6db figure 13. fft plot
ad7683 data sheet rev. b | page 10 of 16 100 95 90 85 80 17 16 15 14 13 2.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 04301-013 reference voltage (v) snr, sinad (db) enob (bits) snr sinad enob figure 14. snr, sinad, and enob vs. reference voltage 100 95 90 85 80 75 70 0 200 150 100 50 04301-014 frequency (khz) sinad (db) v ref = 5v, ?10db v ref = 5v, ?1db v ref = 2.5v, ?1db figure 15. sinad vs. frequency ? 80 ?85 ?90 ?95 ?100 ?105 ?110 0200 120 160 80 40 04301-015 frequency (khz) thd (db) v ref 2.5v = ?1db v ref 5v = ?1db figure 16. thd vs. frequency 1200 1000 800 600 400 200 0 2.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 04301-017 supply (v) operating current (a) f s = 100ksps figure 17. operating current vs. supply
data sheet ad7683 rev. b | page 11 of 16 900 800 700 600 500 400 300 200 100 0 ?55 ?34 ?15 5 25 45 65 85 105 125 04301-018 temperature (c) operating current (a) vdd = 2.7v, f s = 100ksps vdd = 5v, f s = 100ksps figure 18. operating current vs. temperature 1000 750 500 250 0 ?55 ?35 ?15 5 25 45 65 85 105 125 04301-019 temperature (c) power-down current (na) figure 19. power-down current vs. temperature 6 5 4 3 2 1 0 ?1 ?2 ?3 ?4 ?5 ?6 ?55 ?35 ?15 5 25 45 65 85 105 125 04301-016 temperature (c) offset, gain error (lsb) offset error gain error figure 20. offset and gain error vs. temperature
ad7683 data sheet rev. b | page 12 of 16 application s information sw+ msb 16,384c +in lsb comp control logic switches control busy output code cnv ref gnd ?in 4c 2c c c 32,768c sw? msb 16,384c lsb 4c 2c c c 32,768c 04301-020 figure 21 . adc simplified schematic circuit information the ad7683 is a low power, single - supply, 16 - bit adc using a successive approximation architecture. the ad7683 is capable of converting 100,000 samples per second (100 ksps) and powers down between c onversions. when operating at 10 ksps, for example, it consumes typically 150 w with a 2.7 v supply, ideal for battery - powered applications. the ad7683 provides the user with an on - chip track - and - hold and does not exhibit any pipeline delay or latency, making it ideal for multiple, multiplexed channel applications. the ad7683 is specified from 2 .7 v to 5.5 v. it is housed in an 8 - lead msop or a tiny, 8 - lead qfn (lfcsp) package. the ad7683 is an improved second source to the ads8320 and ads8325. for even better performance, consider the ad7685 . converter operation the ad7683 is a successive approximation adc based on a charge redistribution dac. figure 21 shows the simplified schematic of the adc. the capacitive dac consists of two identical arrays of 16 binary - weighted capacitors that connect to the two comparator inputs. during the ac quisition phase, terminals of the array tied to the comparators input are connected to gnd via sw+ and sw?. all independent switches are connected to the analog inputs. thus, the capacitor arrays are used as sampling capacitors and acquire the analog sign al on the +in and ?in inputs. when the acquisition phase is complete and the cs input goes low, a con - version phase is initiated. when the conversion phase begins, sw+ and sw? are opened first. the two capacitor arrays are then disconnect ed from the inputs and connected to the gnd input. therefore, the differential voltage between the inputs, +in and ?in, captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. by switch ing each element of the capacitor array between gnd and ref, the comparator input varies by binary - weighted voltage steps (v ref /2, v ref /4...v ref /65 , 536). the control logic toggles these switches, starting with the msb, to bring the comparator back into a balanced condition. after the completion of t his process, the part returns to the acquisition phase and the control logic generates the adc output code. transfer functions the ideal transfer function for the ad7683 is shown in figure 22 and table 10. 000...000 000...001 000...010 11 1...101 11 1... 1 10 11 1... 11 1 adc code (straight bina r y) analog input +fs ? 1.5 lsb + fs ? 1 lsb ?fs + 1 lsb ?fs ?fs + 0.5 lsb 04301-021 figure 22 . adc ideal transfer function table 10 . output codes and ideal input voltages description analog input v ref = 5 v digital output code hexadecimal fsr C 1 lsb 4.999924 v ffff 1 midscale + 1 lsb 2.500076 v 8001 midscale 2.5 v 8000 midscale C 1 lsb 2.499924 v 7fff C fsr + 1 lsb 76.3 v 0001 C fsr 0 v 0000 2 1 this is also the code for an overranged analog input ( v +in C v C in above v ref C v gnd ). 2 this is also the code for an underranged analog input (v +in C v C in below v gnd ).
data sheet ad7683 rev. b | page 13 of 16 04301-022 ad7683 ref gnd vdd ?in +in dclock d out cs 3-wire interface 100nf 2.7v to 5.25v c ref 2.2f to 10f (note 2) ref 0v to v ref 33 ? 2.7nf (note 3) (note 4) (note 1) notes 1. see voltage reference input section for reference selection. 2. c ref is usually a 10f ceramic capacitor (x5r). 3. see driver amplifier choice section. 4. optional filter. see analog input section. figure 23. typical application diagram typical connection diagram figure 23 shows an example of the recommended application diagram for the ad7683. analog input figure 24 shows an equivalent circuit of the input structure of the ad7683 . the two diodes, d1 and d2, provide esd protec- tion for the analog inputs, +in and ?in. care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 v because this causes these diodes to become forward-biased and start conducting current. however, these diodes can handle a forward-biased current of 130 ma maximum. for instance, these conditions can eventually occur when the input buffer (u1) supplies are different from vdd. in such a case, use an input buffer with a short-circuit current limitation to protect the part. 04301-023 c in r in d1 d2 c pin +in or ?in gnd vdd figure 24. equivalent analog input circuit this analog input structure allows the sampling of the differen- tial signal between +in and ?in. by using this differential input, small signals common to both inputs are rejected. for instance, by using ?in to sense a remote signal ground, ground potential differences between the sensor and the local adc ground are eliminated. during the acquisition phase, the impedance of the analog input, +in, can be modeled as a parallel combination of capacitor c pin and the network formed by the series connection of r in and c in . c pin is primarily the pin capacitance. r in is typically 600 and is a lumped component consisting of some serial resistors and the on resistance of the switches. c in is typically 30 pf and is mainly the adc sampling capacitor. during the conversion phase, when the switches are opened, the input impedance is limited to c pin . r in and c in make a 1-pole, low- pass filter that reduces undesirable aliasing effects and limits the noise. when the source impedance of the driving circuit is low, the ad7683 can be driven directly. large source impedances signi- ficantly affect the ac performance, especially thd. the dc performances are less sensitive to the input impedance. driver amplifier choice although the ad7683 is easy to drive, the driver amplifier needs to meet the following requirements: ? the noise generated by the driver amplifier needs to be kept as low as possible to preserve the snr and transition noise performance of the ad7683 . note that the ad7683 has a noise figure much lower than most other 16-bit adcs and, therefore, can be driven by a noisier op amp while preserving the same or better system performance. the noise coming from the driver is filtered by the ad7683 analog input circuit, 1-pole, low-pass filter made by r in and c in or by the external filter, if one is used. ? for ac applications, the driver needs to have a thd performance suitable to that of the ad7683 . figure 16 shows the thd vs. frequency that the driver should exceed. ? for multichannel multiplexed applications, the driver amplifier and the ad7683 analog input circuit must be able to settle for a full-scale step of the capacitor array at a 16-bit level (0.0015%). in the amplifier data sheet, settling at 0.1% to 0.01% is more commonly specified. this could differ significantly from the settling time at a 16-bit level and should be verified prior to driver selection. table 11. recommended driver amplifiers amplifier typical application ada4841-1 very low noise and low power op184 low power, low noise, and low frequency ad8605, ad8615 5 v single-supply, low power ad8519 low power and low frequency ad8031 high frequency and low power
ad7683 data sheet rev. b | page 14 of 16 voltage reference input the ad7683 voltage reference input, ref, has a dynamic input impedance. therefore, it should be driven by a low impedance source with efficient decoupling between the ref and gnd pins, as explained in the layout section. when ref is driven by a very low impedance source (such as an unbuffered reference voltage like the low temperature drift adr435 reference or a reference buffer using the ad8031 or the ad8605 ), a 10 f (x5r, 0805 size) ceramic chip capacitor is appropriate for optimum performance. if desired, smaller reference decoupling capacitors with values as low as 2.2 f can be used with a minimal impact on perfor- mance, especially dnl. power supply the ad7683 powers down automatically at the end of each conversion phase and, therefore, the power scales linearly with the sampling rate, as shown in figure 25. this makes the part ideal for low sampling rates (even of a few hz) and low battery- powered applications. 1000 100 10 0.1 1 0.01 10 100 1k 10k 100k 04301-024 sampling rate (sps) operating current (a) vdd = 2.7v vdd = 5v figure 25. operating current vs. sampling rate digital interface the ad7683 is compatible with spi?, qspi?, digital hosts, microwire?, and dsps (for example, blackfin? adsp-bf531 , adsp-bf532 , adsp-bf533 , or the adsp-2191m ). the connection diagram is shown in figure 26 and the corresponding timing is given in figure 2. a falling edge on cs initiates a conversion and the data transfer. after the fifth dclock falling edge, d out is enabled and forced low. the data bits are then clocked, msb first, by subsequent dclock falling edges. the data is valid on both dclock edges. although the rising edge can be used to capture the data, a digital host also using the dclock falling edge allows a faster reading rate, provided it has an acceptable hold time. 04301-025 cs dclock d out data in clk convert digital host ad7683 figure 26. connection diagram layout design the pcb that houses the ad7683 so that the analog and digital sections are separated and confined to certain areas of the board. the pin configuration of the ad7683 , with all its analog signals on the left side and all its digital signals on the right side, eases this task. avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the ad7683 is used as a shield. fast switching signals, such as cs or clocks, should never run near analog signal paths. avoid crossover of digital and analog signals. use at least one ground plane. it can be common or split between the digital and analog sections. in such a case, it should be joined underneath the ad7683. the ad7683 voltage reference input (ref) has a dynamic input impedance and should be decoupled with minimal parasitic inductances. accomplish this by placing the reference decoupling ceramic capacitor close to, and ideally right up against, the ref and gnd pins and by connecting these pins with wide, low impedance traces. finally, decouple the power supply, vdd, of the ad7683 with a ceramic capacitor, typically 100 nf, placed close to the ad7683. connect it using short and large traces to provide low impedance paths and reduce the effect of glitches on the power supply lines. evaluating the ad7683 performance other recommended layouts for the ad7683 are outlined in the evaluation board for the ad7683 ( eval-ad7683cbz ). the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the eval-control brd3z.
data sheet ad7683 rev. b | page 15 of 16 outline dimensions compliant to jedec standards mo-187-aa 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 10-07-2009-b figure 27 . 8 - lead mi ni small outline package [msop] (rm - 8) dimensions shown in m illimeters 8 1 5 4 0.35 0.30 0.25 pin 1 index are a se a ting plane 0.80 0.75 0.70 0.20 ref 0.05 max 0.02 nom 0.80 max 0.55 nom 1.74 1.64 1.49 2.48 2.38 2.23 0.50 0.40 0.30 0.65 bsc pin 1 indic a t or (r 0.2) 02-05-2013-c for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. t o p view bottom view 0.20 min exposed pa d 3.10 3.00 sq 2.90 figure 28 . 8 - ter minal quad flat no lead package ( qfn ) [ lfcs p_wd ] 3 mm 3 mm body , very very thin, dual lead (cp - 8 - 3) dimensions shown in m illimeters
ad7683 data sheet rev. b | page 16 of 16 ordering guide model 1 integral nonlinearity temperature range package description 2 package option branding ordering quantity ad7683acpzrl 7 6 lsb max C 40c to +85c 8- lead qfn [lfcsp _wd ] cp -8-3 c4g reel, 1,500 ad7683armz 6 lsb max C 40c to +85c 8- lead msop rm -8 c4g tube, 50 AD7683ARMZRL7 6 lsb max C 40c to +85c 8- lead msop rm -8 c4g reel, 1,000 ad7683bcpzrl 7 3 lsb max C 40c to +85c 8- lead qfn [lfcsp _wd ] cp -8-3 c38 reel, 1,5 00 ad7683brmz 3 lsb max C 40c to +85c 8- lead msop rm -8 c38 tube, 50 ad7683brmzrl7 3 lsb max C 40c to +85c 8- lead msop rm -8 c38 reel, 1,000 eval - ad7683 sd z evaluation board eval - control brd3z controller board 1 z = rohs compliant part. 2 the eval control brd3z board allow s a pc to control and communicate with all analog devices evaluation boards ending in the cb designators. ? 2004 C 2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04301 - 0- 2/16(b)

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